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» Verification of Floating-Point Adders
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ARITH
2009
IEEE
14 years 17 days ago
A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator
The IEEE 754-2008 Standard for Floating-Point Arithmetic was officially approved this year. One of the most
Liang-Kai Wang, Michael J. Schulte
ARITH
2007
IEEE
14 years 3 days ago
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
Liang-Kai Wang, Michael J. Schulte
ARITH
1997
IEEE
13 years 10 months ago
Pipelined Packet-Forwarding Floating Point: II. An Adder
Asger Munk Nielsen, David W. Matula, Chung Nan Lyu...
ICCD
1997
IEEE
115views Hardware» more  ICCD 1997»
13 years 10 months ago
A Low Power Approach to Floating Point Adder Design
R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Kha...
ARITH
2005
IEEE
13 years 11 months ago
High-Radix Implementation of IEEE Floating-Point Addition
We are proposing a micro-architecture for highperformance IEEE floating-point addition that is based on a (non-redundant)high-radix representation of the floatingpoint operands....
Peter-Michael Seidel