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ICCD
2007
IEEE
746views Hardware» more  ICCD 2007»
14 years 2 months ago
Hardware design of a Binary Integer Decimal-based floating-point adder
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...
Charles Tsen, Sonia Gonzalez-Navarro, Michael J. S...
FOCS
2000
IEEE
13 years 10 months ago
Computing the Determinant and Smith Form of an Integer Matrix
A probabilistic algorithm is presented to find the determinant of a nonsingular, integer matrix. For a matrix A ¡£¢ n¤ n the algorithm requires O¥ n3¦5 ¥ logn§ 4¦5§ bit...
Wayne Eberly, Mark Giesbrecht, Gilles Villard
ARITH
2005
IEEE
13 years 11 months ago
N-Bit Unsigned Division via N-Bit Multiply-Add
Integer division on modern processors is expensive compared to multiplication. Previous algorithms for performing unsigned division by an invariant divisor, via reciprocal approxi...
Arch D. Robison
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
13 years 9 months ago
Arithmetic Reasoning in DPLL-Based SAT Solving
We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an arithmetic bit level descrip...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
CODES
2005
IEEE
13 years 11 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...