Sciweavers

304 search results - page 1 / 61
» Verification of Timed Systems Using POSETs
Sort
View
CSREAESA
2004
13 years 6 months ago
Automatic Extraction of Non-Iterated System Behavior from Verilog Specifications
In this paper we present an algorithm for automatic extraction of system behavior from a structural Verilog specification. The algorithm generates a series-parallel poset expressi...
Lubomir Ivanov
CAV
1998
Springer
98views Hardware» more  CAV 1998»
13 years 9 months ago
Verification of Timed Systems Using POSETs
This paper presents a new algorithm for efficiently verifying timed systems. The new algorithm represents timing information using geometric regions and explores the timed state sp...
Wendy Belluomini, Chris J. Myers
CDC
2009
IEEE
151views Control Systems» more  CDC 2009»
13 years 9 months ago
A poset framework to model decentralized control problems
— In this paper we use partially ordered sets (posets) to study decentralized control problems arising in different settings. We show that time delayed systems with certain dela...
Parikshit Shah, Pablo A. Parrilo
ASYNC
1999
IEEE
110views Hardware» more  ASYNC 1999»
13 years 9 months ago
Verification of Delayed-Reset Domino Circuits Using ATACS
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
DATESO
2010
150views Database» more  DATESO 2010»
13 years 2 months ago
Modeling and Verification of Priority Assignment in Real-Time Databases Using Uppaal
Abstract. Real-time database management systems (RTDBMS) are recently subject of an intensive research. Model checking algorithms and verification tools are of great concern as wel...
Martin Kot