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» Verifying an Arbiter Circuit
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IJCAI
1989
13 years 6 months ago
Constraint Posting for Verifying VLSI Circuits
We apply constraint posting to the problem of reasoning about function from structure. Constraint posting is a technique used by some planners to coordinate decisions. At each dec...
Daniel Weise
CCS
2010
ACM
13 years 5 months ago
Modeling attacks on physical unclonable functions
We show in this paper how several proposed Physical Unclonable Functions (PUFs) can be broken by numerical modeling attacks. Given a set of challenge-response pairs (CRPs) of a PU...
Ulrich Rührmair, Frank Sehnke, Jan Sölte...
AROBOTS
2000
108views more  AROBOTS 2000»
13 years 5 months ago
Optimal Selection of Uncertain Actions by Maximizing Expected Utility
A new means of action selection via utility fusion is introduced as an alternative to both sensor fusion and command fusion. Distributed asynchronous behaviors indicate the utility...
Julio Rosenblatt
ITC
2002
IEEE
99views Hardware» more  ITC 2002»
13 years 10 months ago
Verifying Properties Using Sequential ATPG
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
Jacob A. Abraham, Vivekananda M. Vedula, Daniel G....
ASYNC
2005
IEEE
118views Hardware» more  ASYNC 2005»
13 years 11 months ago
Modeling and Verifying Circuits Using Generalized Relative Timing
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Ste...