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» Verifying an Arbiter Circuit
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DAC
1998
ACM
13 years 10 months ago
Buffer Insertion for Noise and Delay Optimization
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
ICC
2007
IEEE
115views Communications» more  ICC 2007»
13 years 10 months ago
Super-Wideband SSN Suppression in High-Speed Digital Communication Systems by Using Multi-Via Electromagnetic Bandgap Structures
With the advance of semiconductor manufacturing, There are many approaches to deal with these problems. EDA, and VLSI design technologies, circuits with even higher Adding discrete...
MuShui Zhang, YuShan Li, LiPing Li, Chen Jia
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
13 years 10 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
EUROCRYPT
2006
Springer
13 years 9 months ago
Our Data, Ourselves: Privacy Via Distributed Noise Generation
In this work we provide efficient distributed protocols for generating shares of random noise, secure against malicious participants. The purpose of the noise generation is to crea...
Cynthia Dwork, Krishnaram Kenthapadi, Frank McSher...
COCOON
2008
Springer
13 years 8 months ago
A Linear Programming Duality Approach to Analyzing Strictly Nonblocking d-ary Multilog Networks under General Crosstalk Constrai
When a switching network topology is used for constructing optical cross-connects, as in the circuit switching case, no two routes are allowed to share a link. However, if two rou...
Hung Q. Ngo, Yang Wang 0014, Anh Le