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» Very Efficient Balanced Codes
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ICIP
1994
IEEE
13 years 9 months ago
Very High Speed Entropy Coding
Efforts to build high-speed hardware for many different entropy coders are limited by fundamental feedback loops. Here is a method that allows for parallel compression in hardware...
Martin P. Boliek, James D. Allen, Edward L. Schwar...
CLUSTER
2007
IEEE
13 years 11 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
PARLE
1987
13 years 8 months ago
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
Peter H. Welch
ASPDAC
2010
ACM
155views Hardware» more  ASPDAC 2010»
13 years 3 months ago
Efficient model reduction of interconnects via double gramians approximation
The gramian approximation methods have been proposed recently to overcome the high computing costs of classical balanced truncation based reduction methods. But those methods typi...
Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yic...
ACL
2004
13 years 6 months ago
Balancing Clarity and Efficiency in Typed Feature Logic Through Delaying
The purpose of this paper is to re-examine the balance between clarity and efficiency in HPSG design, with particular reference to the design decisions made in the English Resourc...
Gerald Penn