26 search results - page 1 / 6 » Virtual Registers: Reducing Register Pressure Without Enlarg... |
HIPEAC
2007
Springer
13 years 11 months ago
2007
Springer
ACSC
2004
IEEE
13 years 8 months ago
2004
IEEE
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce ...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...