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HPCA
1998
IEEE
13 years 9 months ago
Virtual-Physical Registers
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
Antonio González, José Gonzál...
MICRO
2005
IEEE
108views Hardware» more  MICRO 2005»
13 years 11 months ago
How to Fake 1000 Registers
Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading)...
David W. Oehmke, Nathan L. Binkert, Trevor N. Mudg...
CC
2003
Springer
13 years 10 months ago
Early Control of Register Pressure for Software Pipelined Loops
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
Sid Ahmed Ali Touati, Christine Eisenbeis
ICPP
2006
IEEE
13 years 11 months ago
Address-Value Decoupling for Early Register Deallocation
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our ...
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev,...
ASYNC
2004
IEEE
102views Hardware» more  ASYNC 2004»
13 years 9 months ago
Non-Uniform Access Asynchronous Register Files
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
David Fang, Rajit Manohar