While fast timing analysis methods, such as asymptotic waveform evaluation (AWE), have been well established for linear circuits, the timing analysis for non-linear circuits, whic...
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been pr...
Debasish Das, Kip Killpack, Chandramouli V. Kashya...
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...