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COMPUTER
2008
50views more  COMPUTER 2008»
13 years 4 months ago
Warp Processing: Dynamic Translation of Binaries to FPGA Circuits
Frank Vahid, Greg Stitt, Roman L. Lysecky
DAC
2004
ACM
14 years 5 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
13 years 11 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
CODES
2007
IEEE
13 years 11 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
13 years 10 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan