FCCM 2005 - PDF Preprint Papers

FCCM 2005 Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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FCCM
2005
IEEE

155views VLSI» more FCCM 2005»

An Open TCP/IP Core for Reconfigurable Logic

13 years 10 months ago

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Apostolos Dollas, Ioannis Ermis, Iosif Koidis, Ioa...

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Id	Views	Title	Status

1	155	An Open TCP/IP Core for Reconfigurable Logic	claim
2	151	Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems	claim
3	142	FPGA-Based Vector Processing for Solving Sparse Sets of Equations	claim
4	139	A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation	claim
5	132	Hardware Factorization Based on Elliptic Curve Method	claim
6	131	Automating the Layout of Reconfigurable Subsystems Using Circuit Generators	claim
7	124	Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA	claim
8	123	A Novel 2D Filter Design Methodology for Heterogeneous Devices	claim
9	115	FIFO Communication Models in Operating Systems for Reconfigurable Computing	claim
10	113	A Comparison of Floating Point and Logarithmic Number Systems for FPGAs	claim
11	111	A High-Performance Asynchronous FPGA: Test Results	claim
12	107	Hardware Solution to Java Compressed Heap	claim
13	107	Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller	claim
14	106	The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform	claim
15	106	High-Performance FPGA-Based General Reduction Methods	claim
16	102	A Signature Match Processor Architecture for Network Intrusion Detection	claim
17	100	Terrestrial-Based Radiation Upsets: A Cautionary Tale	claim
18	96	A Framework for Rule Processing in Reconfigurable Network Systems	claim
19	96	Preliminary Report: FPGA Acceleration of Molecular Dynamics Computations	claim
20	96	FPGA-Based CDMA Switch for Networks-on-Chip	claim
21	93	Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture	claim
22	90	Optimizing Technology Mapping for FPGAs Using CAMs	claim
23	89	A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms	claim
24	84	Prototyping Architectural Support for Program Rollback Using FPGAs	claim
25	81	Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor	claim
26	73	Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation	claim

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