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DATE
2010
IEEE
164views Hardware» more  DATE 2010»
13 years 10 months ago
On passivity of the super node algorithm for EM modeling of interconnect systems
—The super node algorithm performs model order reduction based on physical principles. Although the algorithm provides us with compact models, its passivity has not thoroughly be...
Maria V. Ugryumova, Wil H. A. Schilders
ASPDAC
2008
ACM
106views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...
Duo Li, Sheldon X.-D. Tan
VLSI
2007
Springer
13 years 11 months ago
Parametric structure-preserving model order reduction
Abstract—Analysis and verification environments for nextgeneration nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects,...
Jorge Fernandez Villena, Wil H. A. Schilders, L. M...
DAC
2003
ACM
13 years 10 months ago
Realizable RLCK circuit crunching
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...