21 search results - page 2 / 5 » WireMap: FPGA technology mapping for improved routability |
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
DAC
1998
ACM
14 years 6 months ago
1998
ACM
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...