564 search results - page 1 / 113 » Wireplanning in logic synthesis |
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
TCAD
1998
13 years 4 months ago
1998
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
EMSOFT
2011
Springer
12 years 4 months ago
2011
Springer
Given a multi-modal dynamical system, optimal switching logic synthesis involves generating conditions for switching between the system modes such that the resulting hybrid system...
NFM
2011
13 years 1 days ago
2011
Synthesis of finite-state machines from linear-time temporal logic (LTL) formulas is an important formal specification debugging technique for reactive systems and can quickly ge...