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» Wiring edge-disjoint layouts
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ASPDAC
1998
ACM
79views Hardware» more  ASPDAC 1998»
13 years 9 months ago
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
Jiang-An He, Hideaki Kobayashi
SOFSEM
2005
Springer
13 years 11 months ago
Volumes of 3D Drawings of Homogenous Product Graphs
d Abstract) Lubomir Torok Institute of Mathematics and Computer Science Slovak Academy of Sciences Severna 5, 974 01 Banska Bystrica, Slovak Republic 3-dimensional layout of graph...
Lubomir Torok
ASPDAC
2008
ACM
86views Hardware» more  ASPDAC 2008»
13 years 7 months ago
An MILP-based wire spreading algorithm for PSM-aware layout modification
Phase shifting mask (PSM) is a promising resolution enhancement technique, which is used in the deep sub-wavelength lithography of the VLSI fabrication process. However, applying ...
Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang
DAC
1996
ACM
13 years 9 months ago
Post-Layout Optimization for Deep Submicron Design
To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...
Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emu...
ICCAD
2002
IEEE
145views Hardware» more  ICCAD 2002»
14 years 2 months ago
A local circuit topology for inductive parasitics
A novel circuit topology for inductive coupling between interconnecting wires is presented. The model is local, i.e., only coupling between neighboring wires is explicitly modeled...
Andrea Pacelli