33 search results - page 7 / 7 » Worst-Case Optimal Tree Layout in a Memory Hierarchy |
GLVLSI
2005
IEEE
13 years 11 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
SIGGRAPH
1996
ACM
13 years 9 months ago
1996
ACM
The result of a scene manipulation is usually displayed by rerendering the entire image even if the change has affected only a small portion of it. This paper presents a system th...
PPOPP
2012
ACM
12 years 24 days ago
2012
ACM
This paper introduces a programming interface called PARRAY (or Parallelizing ARRAYs) that supports system-level succinct programming for heterogeneous parallel systems like GPU c...