4 search results - page 1 / 1 » Wrapper and TAM Co-Optimization for Reuse of SoC Functional ... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of...
ETS
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...