32 search results - page 1 / 7 » Zero-cycle loads: microarchitecture support for reducing loa... |
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
HPCA
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
HPCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
HPCA
2007
IEEE
14 years 5 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...