32 search results - page 2 / 7 » Zero-cycle loads: microarchitecture support for reducing loa... |
ISPASS
2005
IEEE
13 years 10 months ago
2005
IEEE
Communication misses--those serviced by dirty data in remote caches--are a pressing performance limiter in shared-memory multiprocessors. Recent research has indicated that tempor...
HPDC
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper compares the throughput and latency of four protocols that provide total ordering. Two of these protocols are measured with and without message packing. We used a techn...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
AINA
2004
IEEE
13 years 9 months ago
2004
IEEE
Streaming live video over peers in the Internet is gaining popularity since it has the advantage of reducing the load on the server and enable the server to perform other speciali...
NOCS
2010
IEEE
13 years 3 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...