13 search results - page 3 / 3 » aEqualized: A novel routing algorithm for the Spidergon Netw... |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...
DAC
2011
ACM
12 years 4 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
NOCS
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...