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ARITH
1999
IEEE
13 years 9 months ago
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition
In two operand addition, bit-wise intermediate variables such as the "propagate" and "generate" terms are defined/evaluated first. Basic carry propagation recu...
Dhananjay S. Phatak, Israel Koren
ARITH
1999
IEEE
13 years 9 months ago
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm i...
Guy Even, Peter-Michael Seidel
ARITH
1999
IEEE
13 years 9 months ago
On the Design of High-Radix On-Line Division for Long Precision
We present a design of a high-radix on-line division suitable for long precision computations. The proposed scheme uses a quotient-digit selection function based on the residual r...
Alexandre F. Tenca, Milos D. Ercegovac
ARITH
1999
IEEE
13 years 9 months ago
Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16
Although division is less frequent than addition and multiplication, because of its longer latency it dissipates a substantial part of the energy in floating-point units. In this ...
Alberto Nannarelli, Tomás Lang
ARITH
1999
IEEE
13 years 9 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...