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ASAP
2006
IEEE
150views Hardware» more  ASAP 2006»
13 years 7 months ago
Architecture design of an H.264/AVC decoder for real-time FPGA implementation
This paper discusses hardware development of a realtime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse t...
Thomas Warsaw, Marcin Lukowiak
ASAP
2006
IEEE
89views Hardware» more  ASAP 2006»
13 years 9 months ago
Polyhedral Modeling and Analysis of Memory Access Profiles
In this paper, we propose to model memory access profile information as loop nests exhibiting useful characteristics on the memory behavior, such as periodicity, linearly linked m...
Philippe Clauss, Bénédicte Kenmei
ASAP
2006
IEEE
169views Hardware» more  ASAP 2006»
13 years 11 months ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben...
ASAP
2006
IEEE
162views Hardware» more  ASAP 2006»
13 years 9 months ago
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts
Parameterized static affine nested loop programs can be automatically converted to input-output equivalent Kahn Process Network specifications. These networks turn out to be close...
Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhatta...
ASAP
2006
IEEE
131views Hardware» more  ASAP 2006»
13 years 9 months ago
A Generic Multi-Phase On-Chip Traffic Generation Environment
We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three importan...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset