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ASAP
2007
IEEE
144views Hardware» more  ASAP 2007»
13 years 11 months ago
A High-Throughput Programmable Decoder for LDPC Convolutional Codes
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
Marcel Bimberg, Marcos B. S. Tavares, Emil Mat&uac...
ASAP
2007
IEEE
116views Hardware» more  ASAP 2007»
13 years 7 months ago
The Design of a Novel Object-oriented Processor : OOMIPS
A novel object-oriented processor is proposed in this paper, which provides support for object addressing, message passing and dynamic memory management. Object running on this pr...
Weixing Ji, Feng Shi, Baojun Qiao, Muhammad Kamran
ASAP
2007
IEEE
93views Hardware» more  ASAP 2007»
13 years 11 months ago
LNS Subtraction Using Novel Cotransformation and/or Interpolation
The Logarithmic Number System (LNS) makes multiplication, division and powering easy, but subtraction is expensive. Cotransformation converts the difficult operation of logarithm...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
13 years 9 months ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
ASAP
2007
IEEE
130views Hardware» more  ASAP 2007»
13 years 9 months ago
A Self-Reconfigurable Implementation of the JPEG Encoder
Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a ...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...