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ATS
2000
IEEE
149views Hardware» more  ATS 2000»
13 years 9 months ago
Efficient built-in self-test algorithm for memory
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
Sying-Jyan Wang, Chen-Jung Wei
ICCAD
2000
IEEE
77views Hardware» more  ICCAD 2000»
13 years 9 months ago
Improving the Proportion of At-Speed Tests in Scan BIST
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janus...
ATS
2000
IEEE
107views Hardware» more  ATS 2000»
13 years 9 months ago
Accumulation-based concurrent fault detection for linear digital state variable systems
An algorithmic fault detection scheme for linear digital state variable systems is proposed. The proposed scheme eliminates the necessity of observing the internal states of the s...
Ismet Bayraktaroglu, Alex Orailoglu
ATS
2000
IEEE
116views Hardware» more  ATS 2000»
13 years 9 months ago
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
: In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed i...
Said Hamdioui, A. J. van de Goor
ATS
2000
IEEE
149views Hardware» more  ATS 2000»
13 years 9 months ago
Charge sharing fault analysis and testing for CMOS domino logic circuits
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Sh...