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CSREAESA
2003
10 years 11 months ago
Verification Patterns for Rapid Embedded System Verification
Wei-Tek Tsai, Feng Zhu, Lian Yu, Raymond A. Paul, ...
CSREAESA
2003
10 years 11 months ago
Design of Digital Circuits on the Basis of Hardware Templates
The paper presents a technique for the design of digital circuits based on reusable hardware templates (HT). Any HT is being constructed in such a way that it might be employed for...
Valery Sklyarov, Iouliia Skliarova
CSREAESA
2003
10 years 11 months ago
Low-Power Dynamic Scheduling in Heterogeneous Systems
: This paper develops a matching and scheduling algorithm that accounts for both the execution time and the power consumption of the application. The power consumption of different...
Saumya Uppaluri, Baback A. Izadi, Damu Radhakrishn...
CSREAESA
2003
10 years 11 months ago
Power Optimized Combinational Logic Design
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
CSREAESA
2003
10 years 11 months ago
Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems
We present an approach for Worst-Case Execution Time (WCET) Analysis of embedded system software, that is generated from Petri net speciļ¬cations. The presented approach is part ...
Friedhelm Stappert, Carsten Rust
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