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DFT
1999
IEEE
80views VLSI» more  DFT 1999»
13 years 9 months ago
Determination of Yield Bounds Prior to Routing
Integrated Circuit manufacturing complexities have resulted in decreasing product yields and reliabilities. This process has been accelerated with the advent of very deep sub-micr...
Arunshankar Venkataraman, Israel Koren
ATS
1999
IEEE
99views Hardware» more  ATS 1999»
13 years 9 months ago
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets
Abhijit Jas, Kartik Mohanram, Nur A. Touba
ISCAS
1999
IEEE
87views Hardware» more  ISCAS 1999»
13 years 9 months ago
Asymptotical optimality of DFT based DMT transceivers
The DMT (discrete multitone modulation) technique has been widely applied to data transmission over fading channels of twisted pairs. It has been shown that the DMT system with id...
Yuan-Pei Lin, See-May Phoong
DFT
1999
IEEE
72views VLSI» more  DFT 1999»
13 years 9 months ago
Yield Estimation of VLSI Circuits with Downscaled Layouts
This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design whi...
Witold A. Pleskacz
DFT
1999
IEEE
125views VLSI» more  DFT 1999»
13 years 9 months ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...