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DSD
2007
IEEE
13 years 8 months ago
2007
IEEE
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...