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DSD
2009
IEEE
85views Hardware» more  DSD 2009»
14 years 16 days ago
Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment
—Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating duri...
Zhiyuan He, Zebo Peng, Petru Eles
DSD
2009
IEEE
147views Hardware» more  DSD 2009»
13 years 9 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu
DSD
2009
IEEE
93views Hardware» more  DSD 2009»
13 years 3 months ago
Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
Antonio da Silva, Sebastian Sanchez
DSD
2009
IEEE
77views Hardware» more  DSD 2009»
14 years 16 days ago
Pulse Generation for On-chip Data Transmission
Abstract—Pulse-based data transmission has been demonstrated as a power-saving and high performance alternative to level-based signalling over global distances. Key to its correc...
Simon Hollis
DSD
2009
IEEE
90views Hardware» more  DSD 2009»
14 years 16 days ago
Instruction Precomputation for Fault Detection
—Fault tolerance (FT) is becoming increasingly important in computing systems. This work proposes and evaluates the instruction precomputation technique to detect hardware faults...
Demid Borodin, Ben H. H. Juurlink, Stefanos Kaxira...