Sciweavers

27 search results - page 3 / 6
» dsd 2010
Sort
View
DSD
2010
IEEE
162views Hardware» more  DSD 2010»
13 years 3 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...
DSD
2010
IEEE
135views Hardware» more  DSD 2010»
13 years 5 months ago
An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits
—This paper presents an approximate Maximum Common Subgraph (MCS) algorithm, specifically for directed, cyclic graphs representing digital circuits. Because of the application d...
Jochem H. Rutgers, Pascal T. Wolkotte, Philip K. F...
DSD
2010
IEEE
121views Hardware» more  DSD 2010»
13 years 2 months ago
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA
Orthogonal Frequency Division Multiplexing (OFDM) can provide a flexible usage of the spectrum by controlling individual subcarriers. Sets of subcarriers can be zero-modulated to a...
Adolfo Recio, Peter M. Athanas
DSD
2010
IEEE
110views Hardware» more  DSD 2010»
13 years 5 months ago
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour
—The design of new embedded systems is getting more and more complex as more functionality is integrated into these systems. To deal with the design complexity, a predictable des...
Sander Stuijk, Marc Geilen, Twan Basten
DSD
2010
IEEE
161views Hardware» more  DSD 2010»
13 years 5 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana