Sciweavers

34 search results - page 2 / 7
» ersa 2006
Sort
View
ERSA
2006
114views Hardware» more  ERSA 2006»
13 years 6 months ago
Architectural Support for Runtime 2D Partial Reconfiguration
: Traditional FPGA architectures can potentially allow the dynamic swap in and out of hardware tasks through 2D partial reconfiguration. A segmented bus structure is proposed to be...
Fei Wang, Jack S. N. Jean
ERSA
2006
98views Hardware» more  ERSA 2006»
13 years 6 months ago
Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array
To date, some types of Optically Reconfigurable Gate Arrays (ORGAs) have been developed to realize capabilities of rapid reconfiguration with numerous reconfiguration contexts. How...
Minoru Watanabe, Fuminori Kobayashi
ERSA
2006
76views Hardware» more  ERSA 2006»
13 years 6 months ago
Logic Synthesis and Place-and-Route Environment for ORGAs
Abstract-- We have continued development of Optically Reconfigurable Gate Arrays (ORGAs) to realize larger virtual gate count VLSIs than currently available VLSIs. The grain and st...
Minoru Watanabe, Fuminori Kobayashi
ERSA
2006
105views Hardware» more  ERSA 2006»
13 years 6 months ago
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
ERSA
2006
91views Hardware» more  ERSA 2006»
13 years 6 months ago
Intrinsic Embedded Hardware Evolution of Block-based Neural Networks
- An intrinsic embedded online evolution system has been designed using Block-based neural networks and implemented on Xilinx VirtexIIPro FPGAs. The designed network can dynamicall...
Saumil Merchant, Gregory D. Peterson, Seong Kong