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EURODAC
1995
IEEE
133views VHDL» more  EURODAC 1995»
13 years 8 months ago
Tree restructuring approach to mapping problem in cellular-architecture FPGAs
A new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity a...
Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Nav...
EURODAC
1995
IEEE
202views VHDL» more  EURODAC 1995»
13 years 8 months ago
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
Distributed systems are becoming a popular way of implementing many embedded computing applications, automotive control being a common and important example. Such embedded systems...
Santhanam Srinivasan, Niraj K. Jha
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
13 years 8 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
EURODAC
1995
IEEE
101views VHDL» more  EURODAC 1995»
13 years 8 months ago
Exploiting power-up delay for sequential optimization
Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K....
EURODAC
1995
IEEE
112views VHDL» more  EURODAC 1995»
13 years 8 months ago
On implementation choices for iterative improvement partitioning algorithms
Iterative improvement partitioning algorithms such as the FM algorithm of Fiduccia and Mattheyses 8 , the algorithm of Krishnamurthy 13 , and Sanchis's extensions of these al...
Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng