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EURODAC
1995
IEEE
182views VHDL» more  EURODAC 1995»
13 years 9 months ago
Delay modelling improvement for low voltage applications
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
Jean Michel Daga, Michel Robert, Daniel Auvergne
EURODAC
1995
IEEE
127views VHDL» more  EURODAC 1995»
13 years 9 months ago
Layout synthesis for datapath designs
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charle...
EURODAC
1995
IEEE
142views VHDL» more  EURODAC 1995»
13 years 9 months ago
Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics
Because it costs to solve ElectroMagnetic Compatibility (EMC) problems late in the development process, new methods have to predict radiated electromagnetic emissions at the desig...
E. Leroux, Flavio G. Canavero, G. Vecchi
EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
13 years 9 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
13 years 9 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...