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FMCAD
2008
Springer
13 years 6 months ago
Scaling Up the Formal Verification of Lustre Programs with SMT-Based Techniques
We present a general approach for verifying safety properties of Lustre programs automatically. Key aspects of the approach are the choice of an expressive first-order logic in wh...
George Hagen, Cesare Tinelli
FMCAD
2008
Springer
13 years 6 months ago
Augmenting a Regular Expression-Based Temporal Logic with Local Variables
The semantics of temporal logic is usually defined with respect to a word representing a computation path over a set of atomic propositions. A temporal logic formula does not contr...
Cindy Eisner, Dana Fisman
FMCAD
2008
Springer
13 years 6 months ago
Recording Synthesis History for Sequential Verification
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...
Alan Mishchenko, Robert K. Brayton
FMCAD
2008
Springer
13 years 6 months ago
Mechanized Information Flow Analysis through Inductive Assertions
We present a method for verifying information flow properties of software programs using inductive assertions and theorem proving. Given a program annotated with information flow a...
Warren A. Hunt Jr., Robert Bellarmine Krug, Sandip...
FMCAD
2008
Springer
13 years 6 months ago
Scheduling Optimisations for SPIN to Minimise Buffer Requirements in Synchronous Data Flow
Synchronous Data flow (SDF) graphs have a simple and elegant semantics (essentially linear algebra) which makes SDF graphs eminently suitable as a vehicle for studying scheduling o...
Pieter H. Hartel, Theo C. Ruys, Marc C. W. Geilen