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ASPDAC
2001
ACM
120views Hardware» more  ASPDAC 2001»
13 years 9 months ago
Virtual Java/FPGA interface for networked reconfiguration
Abstract- Avirtual interfacebetweenJava andFPGA for networked reconfigurationis presented. ThroughtheJavaflFPGAinterface,Java applicationscan exploithardwareaccelerators with FPGAs...
Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, S...
ISW
2001
Springer
13 years 10 months ago
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator B
In this paper, we present the results of the first phase of a project aimed at implementing a full suite of IPSec cryptographic transformations in reconfigurable hardware. Full imp...
Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Sc...
FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
13 years 10 months ago
Mixing buffers and pass transistors in FPGA routing architectures
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
Mike Sheng, Jonathan Rose
DAC
2001
ACM
14 years 6 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
14 years 2 months ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...