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JSA
2011
76views more  JSA 2011»
8 years 5 months ago
Transactional memories for multi-processor FPGA platforms
Christoforos Kachris, Chidamber Kulkarni
FPGA
2011
ACM
321views FPGA» more  FPGA 2011»
8 years 1 months ago
An analytical model relating FPGA architecture parameters to routability
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch b...
Joydip Das, Steven J. E. Wilton
ASPDAC
2011
ACM
215views Hardware» more  ASPDAC 2011»
8 years 1 months ago
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...
ICASSP
2011
IEEE
8 years 1 months ago
FPGA implementation made easy for applied digital signal processing courses
Applied digital signal processing courses offered at many universities do not normally include FPGA implementation of signal processing algorithms. This is due to the fact that st...
Nasser D. Kehtarnavaz, Sidharth Mahotra
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