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FPL
2005
Springer
89views Hardware» more  FPL 2005»
13 years 11 months ago
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
FPL
2005
Springer
110views Hardware» more  FPL 2005»
13 years 11 months ago
CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools
Abstract. We propose CUSTARD — CUStomisable Threaded ARchitecture — a soft processor design space that combines support for multiple hardware threads and automatically generate...
Robert G. Dimond, Oskar Mencer, Wayne Luk
FPL
2005
Springer
107views Hardware» more  FPL 2005»
13 years 11 months ago
Programmable Numerical Function Generators: Architectures and Synthesis Method
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal,...
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
FPL
2005
Springer
130views Hardware» more  FPL 2005»
13 years 11 months ago
Communication Synthesis in a multiprocessor environment
At Leiden University, we are developing a design methodology that allows for fast mapping of nested-loop applications (e.g. DSP, Imaging, or MultiMedia) written in a subset of Matl...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
FPL
2005
Springer
112views Hardware» more  FPL 2005»
13 years 11 months ago
Hierarchical Placement for Large-scale FPAA
Abstract— Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness...
I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David...