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34

GLVLSI
2007
IEEE

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I-cache multi-banking and vertical interleaving

13 years 11 months ago

I-cache multi-banking and vertical interleaving

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Sangyeun Cho

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11

GLVLSI
2007
IEEE

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Improvements for constraint solving in the systemc verification library

13 years 11 months ago

Improvements for constraint solving in the systemc verification library

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Daniel Große, Rüdiger Ebendt, Rolf Drec...

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12

GLVLSI
2007
IEEE

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Optimization techniques for BDD-based bisimulation computation

13 years 11 months ago

Optimization techniques for BDD-based bisimulation computation

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Ralf Wimmer, Marc Herbstritt, Bernd Becker

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13

GLVLSI
2007
IEEE

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An asynchronous fpga logic cell implementation

13 years 8 months ago

An asynchronous fpga logic cell implementation

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Atabak Mahram, Mehrdad Najibi, Hossein Pedram

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12

GLVLSI
2007
IEEE

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Three-valued automated reasoning on analog properties

13 years 6 months ago

Three-valued automated reasoning on analog properties

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Raffaella Gentilini, Klaus Schneider, Alexander Dr...

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