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HOTI
2005
IEEE
13 years 10 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
HOTI
2005
IEEE
13 years 10 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner
HOTI
2005
IEEE
13 years 10 months ago
Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication
Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bo...
Robert J. Drost, Craig Forrest, Bruce Guenin, Ron ...
HOTI
2005
IEEE
13 years 10 months ago
Zero Copy Sockets Direct Protocol over InfiniBand - Preliminary Implementation and Performance Analysis
Sockets Direct Protocol (SDP) is a byte-stream transport protocol implementing the TCP SOCK_STREAM semantics utilizing transport offloading capabilities of the InfiniBand fabric. ...
Dror Goldenberg, Michael Kagan, Ran Ravid, Michael...
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HOTI
2005
IEEE
13 years 10 months ago
Design and Implementation of a Content-Aware Switch Using a Network Processor
Cluster based server architectures have been widely used as a solution to overloading in web servers because of their cost effectiveness, scalability and reliability. A content aw...
Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. ...