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HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
HPCA
2009
IEEE
14 years 11 days ago
2009
IEEE
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
HPCA
2009
IEEE
14 years 11 days ago
2009
IEEE
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can targ...