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10

ICCAD
1996
IEEE

106views Hardware» more ICCAD 1996»

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

13 years 10 months ago

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

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Takumi Okamoto, Jason Cong

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10

ICCAD
1996
IEEE

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Using complete-1-distinguishability for FSM equivalence checking

13 years 10 months ago

Using complete-1-distinguishability for FSM equivalence checking

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Pranav Ashar, Aarti Gupta, Sharad Malik

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9

ICCAD
1996
IEEE

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ACV: an arithmetic circuit verifier

13 years 10 months ago

ACV: an arithmetic circuit verifier

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Yirng-An Chen, Randal E. Bryant

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10

ICCAD
1996
IEEE

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Logic optimization by output phase assignment in dynamic logic synthesis

13 years 10 months ago

Logic optimization by output phase assignment in dynamic logic synthesis

Download www.cs.nthu.edu.tw

Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser

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10

ICCAD
1996
IEEE

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Stratified random sampling for power estimation

13 years 10 months ago

Stratified random sampling for power estimation

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Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu, Massoud P...

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