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ICCAD
1997
IEEE
118views Hardware» more  ICCAD 1997»
13 years 9 months ago
Global interconnect sizing and spacing with consideration of coupling capacitance
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...
Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang P...
ICCAD
1997
IEEE
122views Hardware» more  ICCAD 1997»
13 years 9 months ago
Approximate timing analysis of combinational circuits under the XBD0 model
This paper is concerned with approximate delay computation algorithms for combinational circuits. As a result of intensive research in the early 90’s [3, 8] efficient tools exi...
Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, R...
ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
13 years 9 months ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
ICCAD
1997
IEEE
86views Hardware» more  ICCAD 1997»
13 years 9 months ago
Interconnect design for deep submicron ICs
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok K...
ICCAD
1997
IEEE
112views Hardware» more  ICCAD 1997»
13 years 9 months ago
Circuit optimization via adjoint Lagrangians
The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the o...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...