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ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip...
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be fo...