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iccad 2009
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ICCAD
2009
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A study of Through-Silicon-Via impact on the 3D stacked IC layout
13 years 7 months ago
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Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
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Joint design-time and post-silicon optimization for digitally tuned analog circuits
13 years 7 months ago
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eda.ee.ucla.edu
Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti
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IPR: In-Place Reconfiguration for FPGA fault tolerance
13 years 7 months ago
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Zhe Feng 0002, Yu Hu, Lei He, Rupak Majumdar
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Synthesizing complementary circuits automatically
13 years 7 months ago
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ShengYu Shen, Jianmin Zhang, Ying Qin, Sikun Li
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Timing Arc based logic analysis for false noise reduction
13 years 7 months ago
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The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it ...
Murthy Palla, Jens Bargfrede, Stephan Eggersgl&uum...
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