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ICCD
2007
IEEE
106views Hardware» more  ICCD 2007»
13 years 9 months ago
Transparent mode flip-flops for collapsible pipelines
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...
Eric L. Hill, Mikko H. Lipasti
ICCD
2007
IEEE
152views Hardware» more  ICCD 2007»
13 years 9 months ago
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
13 years 9 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
ICCD
2007
IEEE
183views Hardware» more  ICCD 2007»
14 years 2 months ago
Constraint satisfaction in incremental placement with application to performance optimization under power constraints
We present new techniques for explicit constraint satisfaction in the incremental placement process. Our algorithm employs a Lagrangian Relaxation (LR) type approach in the analyt...
Huan Ren, Shantanu Dutt
ICCD
2007
IEEE
121views Hardware» more  ICCD 2007»
14 years 2 months ago
Fast power network analysis with multiple clock domains
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Z...