28 search results - page 6 / 6 » ieeepact 2000 |
IEEEPACT
2006
IEEE
13 years 10 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
IEEEPACT
2002
IEEE
13 years 9 months ago
2002
IEEE
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...
IEEEPACT
1999
IEEE
13 years 9 months ago
1999
IEEE
The performance of applications on large shared-memory multiprocessors with coherent caches depends on the interaction between the granularity of data sharing, the size of the coh...