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1999
Tsinghua U.
13 years 9 months ago
Reorganizing global schedules for register allocation
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
Gang Chen, Michael D. Smith
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
13 years 9 months ago
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions
This paper aims to provide a quantitative understanding of the performance of image and video processing applications on general-purpose processors, without and with media ISA ext...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
ILP
1999
Springer
13 years 9 months ago
Probabilistic Relational Models
Most real-world data is heterogeneous and richly interconnected. Examples include the Web, hypertext, bibliometric data and social networks. In contrast, most statistical learning...
Daphne Koller
ILP
1999
Springer
13 years 9 months ago
Rule Evaluation Measures: A Unifying View
Numerous measures are used for performance evaluation in machine learning. In predictive knowledge discovery, the most frequently used measure is classification accuracy. With new...
Nada Lavrac, Peter A. Flach, Blaz Zupan
ITC
1999
IEEE
107views Hardware» more  ITC 1999»
13 years 9 months ago
A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
Han Bin Kim, Dong Sam Ha