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ISCA
1997
IEEE
119views Hardware» more  ISCA 1997»
13 years 8 months ago
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference
Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction acc...
Eric Sprangle, Robert S. Chappell, Mitch Alsup, Ya...
ISCA
1997
IEEE
98views Hardware» more  ISCA 1997»
13 years 8 months ago
Target Prediction for Indirect Jumps
As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be th...
Po-Yung Chang, Eric Hao, Yale N. Patt
ICCAD
1997
IEEE
108views Hardware» more  ICCAD 1997»
13 years 9 months ago
Fault simulation of interconnect opens in digital CMOS circuits
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
Haluk Konuk
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
13 years 9 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
13 years 9 months ago
A Language for Describing Predictors and Its Application to Automatic Synthesis
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
Joel S. Emer, Nicholas C. Gloy