Fault simulation of interconnect opens in digital CMOS circuits

We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four different factors, that can a ect the voltage of an open, into account; and considering the oscillation and sequential behavior potential of opens. A novel test technique based on controlling the die surface voltage is also described. We present simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets.

• Type: Conference
• Year: 1997
• Where: ICCAD
• Authors: Haluk Konuk
• Keywords: Cient Fault Simulator, Die Surface Voltage, Hardware, ICCAD 1997, Transistor Charge Equations