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TCAD
2008
13 years 5 months ago
2008
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
TCAD
2008
13 years 5 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
TCAD
2008
13 years 5 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
TCAD
2008
13 years 5 months ago
2008
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
ICCD
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...