Sciweavers

27 search results - page 3 / 6
» isca 2012
Sort
View
ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
11 years 7 months ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...
ISCA
2012
IEEE
237views Hardware» more  ISCA 2012»
11 years 7 months ago
BOOM: Enabling mobile memory based low-power server DIMMs
To address the real-time processing needs of large and growing amounts of data, modern software increasingly uses main memory as the primary data store for critical information. T...
Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar...
ISCA
2012
IEEE
191views Hardware» more  ISCA 2012»
11 years 7 months ago
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors
Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy e...
Timothy N. Miller, Renji Thomas, Xiang Pan, Radu T...
ISCA
2012
IEEE
218views Hardware» more  ISCA 2012»
11 years 7 months ago
Towards energy-proportional datacenter memory with mobile DRAM
To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high b...
Krishna T. Malladi, Frank A. Nothaft, Karthika Per...
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
11 years 7 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...